Quantum Tunneling: When Transistors Get Too Small

Classical and Quantum Descriptions of Electron Behaviour

In classical mechanics, a particle with energy E cannot penetrate a potential barrier of height V when V exceeds E. The particle's kinetic energy would become negative within the barrier region, which is physically impossible in a classical framework. The electron simply reflects from the barrier boundary and proceeds no further.

In quantum mechanics, the situation is fundamentally different. The electron's state is described not by a definite position and velocity, but by a wave function — a probability amplitude that evolves according to the Schrödinger equation. When a quantum particle encounters a finite potential barrier, its wave function does not abruptly vanish at the barrier boundary. Instead, it decays exponentially into the classically forbidden region, and if the barrier is sufficiently thin, the wave function retains non-zero amplitude on the far side. This residual amplitude represents a finite probability that the particle will be found beyond the barrier without having possessed the classical energy required to surmount it. This phenomenon is quantum mechanical tunnelling.

Tunnelling in Gate Dielectrics

The relevance of quantum tunnelling to transistor design arises in the gate dielectric — the thin insulating layer between the metallic gate electrode and the silicon channel region beneath. In a MOSFET operating in the off state, the gate dielectric is intended to function as an insulating barrier preventing current flow from the gate to the channel. In classical electrostatics, a silicon dioxide layer of any finite thickness should prevent all gate leakage current at operating voltages below the breakdown threshold of the material (approximately 10 MV/cm for SiO₂).

In practice, at thicknesses below approximately 3 nm, direct tunnelling current through the gate oxide becomes measurable. At 1.5 nm thickness — approximately five monolayers of silicon dioxide — the oxide tunnelling current density can reach several amperes per square centimetre at moderate operating voltages, representing a catastrophic leakage contribution to standby power. At 1.2 nm, the barrier is too thin for the oxide to function as an insulator by any practical metric.

"The gate dielectric is not simply a material engineering problem; at sub-2nm thicknesses, it is a quantum physics problem with a material engineering constraint." — adapted from Muller et al., Nature, 1999

Types of Tunnelling Current in MOSFETs

The literature distinguishes several distinct tunnelling mechanisms in sub-100 nm MOSFETs. Direct tunnelling dominates when the oxide thickness is below approximately 3 nm and operating voltage is below the barrier height: the electron tunnels directly through the triangular or trapezoidal potential profile of the oxide. Fowler-Nordheim tunnelling occurs at higher electric fields, where the effective barrier seen by the electron is triangular (rather than trapezoidal), and governs charge injection in non-volatile memory devices such as Flash EEPROM.

A second category of tunnelling — sub-threshold source-to-drain tunnelling — becomes relevant as the physical channel length itself approaches sub-5 nm dimensions. At these scales, an electron near the source end of the channel may tunnel directly to the drain without traversing the channel classically. This mechanism sets an absolute physical lower bound on transistor gate length regardless of dielectric quality, because it cannot be mitigated by material substitution. Theoretical estimates place this fundamental limit in the range of 3 to 5 nm for silicon channels, though alternative channel materials with larger effective masses (which reduce tunnelling probability) may extend the boundary somewhat.

Material Responses: High-k Dielectrics

The engineering response to direct gate oxide tunnelling exploits a fundamental relationship in electrostatics: the capacitance per unit area of a dielectric is proportional to its dielectric constant k and inversely proportional to its physical thickness. By replacing silicon dioxide (k ≈ 3.9) with a material of higher dielectric constant, a physically thicker insulating layer can deliver the same gate-channel capacitance — and thus the same transistor switching performance — with exponentially lower tunnelling current, since tunnelling probability falls exponentially with increasing physical barrier thickness.

Hafnium oxide (HfO₂, k ≈ 20–25) was the first commercially deployed high-k gate dielectric, introduced in the Intel 45 nm generation (2007). A hafnium oxide layer of 2–3 nm physical thickness achieves an equivalent oxide thickness (EOT) of approximately 0.5–0.8 nm while reducing gate leakage by three to four orders of magnitude compared to a silicon dioxide layer of equivalent capacitance. Subsequent process generations have refined the hafnium oxide composition through alloying with silicon, nitrogen, and lanthanum to optimise the dielectric constant, thermal stability, and interface quality simultaneously.

Three-Dimensional Transistor Geometries as a Quantum Response

The FinFET architecture — first commercialised in the Intel 22 nm generation (2012) — addresses quantum leakage through geometric rather than purely material innovation. By extending the silicon channel into a thin vertical fin and wrapping the gate electrode around three surfaces of this fin, the FinFET increases the electrostatic control that the gate exerts over the channel. This enhanced gate control, measured by the subthreshold swing (the rate at which drain current falls per decade of gate voltage reduction below threshold), allows the transistor to switch off more sharply and reduces sub-threshold leakage current — though it does not directly mitigate quantum mechanical source-to-drain tunnelling in the shortest channel devices.

The gate-all-around nanosheet transistor, now entering commercial production at the 3 nm generation, extends this principle to four-sided gate wrapping of multiple stacked silicon nanosheets, achieving the strongest possible electrostatic confinement available in a silicon channel geometry. Whether further transistor scaling beyond approximately 2 nm effective gate length is achievable in silicon remains an open research question in the semiconductor physics literature.